Cnuas Calibrated Virtual-time and Performance Model¶
cnuas-timing gives Cnuas a deterministic, cross-component model-time
calculation without treating host execution speed as simulated hardware speed.
It can answer questions such as:
- How much analytic service time does this packet, transfer, kernel, or Modbus frame consume?
- Where does queueing occur when jobs share a NIC, switch, accelerator, or bus?
- Which resource limits a pipeline as packet size, tensor size, or arrival rate changes?
- How does an analytic estimate compare with measurements from a named physical target?
- What error remains on workloads that were not used to fit the model?
The current release evaluates explicit pipelines offline. It does not yet synchronize the live clocks of QEMU, Renode, or host daemons. The supplied profile is analytic and uncalibrated, so its output is not a physical hardware performance claim.
Choose a starting point¶
| Goal | Read |
|---|---|
| Understand why the model exists | Concepts and evidence |
| Install it and run the example | Quick start |
| Understand the scheduler and equations | Architecture and algorithm |
| Create or change component profiles | Profiles and pipelines |
| Fit a physical target and measure error | Calibration and validation |
| Use every CLI command or the Python API | CLI and Python reference |
| Follow component-specific examples | Worked examples |
| Decide what a result permits you to claim | Limits and interpretation |
| Read the product summary | Datasheet |
What is implemented¶
flowchart LR
W[Work inputs] --> P[Pipeline stages]
R[Versioned component profile] --> S[Picosecond scheduler]
P --> S
S --> T[Event trace]
T --> M[Latency throughput queue metrics]
H[Hardware training observations] --> C[Affine calibration]
M --> C
C --> CP[Named calibrated component]
V[Held-out observations] --> E[MAE RMSE MAPE max error]
CP --> E
| Capability | State |
|---|---|
| Analytic component service times | Available |
| Deterministic queue and lane scheduler | Available |
| End-to-end explicit pipelines | Available |
QEMU icount argument and instruction-time mapping |
Available |
| Target-specific affine fitting | Available |
| Held-out error reporting | Available |
| Runtime trace ingestion | Planned |
| Live QEMU, Renode, and daemon clock federation | Planned |
| Published physical target profiles | Planned |
Component coverage¶
The reference profile spans the Cnuas system rather than one device:
| Component | Modelled work |
|---|---|
| Guest processor | Instructions under a selected QEMU icount shift |
| PCIe Gen5 x16 | Transfer bytes |
| CnuasNIC | Packet and byte service |
| CnuasSwitch | Per-hop packet and byte service |
| CnuasGPU | Compute operations, tile cycles, memory bytes, parallel lanes |
| CnuasLink | Frame transfer and fixed hop cost |
| CnuasBMC | ORV3 Modbus RTU frame transfer at 19,200 baud |
| Facility control | Telemetry and power-roll-up cadence |
Values fixed by a protocol are identified as such. Illustrative latency, bandwidth, and throughput assumptions are labelled in the profile notes.
Source and outputs¶
| Artefact | Location |
|---|---|
| Python package | timing/src/cnuas_timing/ |
| Analytic profile | timing/profiles/cnuas-analytic-v0.json |
| Example pipeline | timing/examples/rdma-gpu-pipeline.json |
| Tests | timing/tests/ |
| Dedicated paper | academicresearch/publications/cnuas-timing/ in the academic-research repository |
| Datasheet PDF | Generated from docs/datasheets/Cnuas_Timing_Datasheet.md |